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[Embeded-SCM Develop] avrx

Description: 血凝仪检测系统,硬件电路部分由正弦波产生模块、前级放大与滤波模块、检测线圈、锁相环同步检波模块、后级平滑滤波与放大模块、AD转换器、线圈驱动模块、单片机模块等部分组成。-Coagulometer detection system, the hardware circuit sine wave generated by the module, pre-amplification and filtering module, detection coil, phase-locked loop synchronous detector modules, after-class smoothing filtering and amplification modules, AD converter, coil drive module, single-chip modules, such as machine parts.
Platform: | Size: 95232 | Author: 韦编三绝 | Hits:

[Other] H9200

Description: H9200是一款商品防盗EAS主板,用于商场、服装，超市等场所的防盗产品，本产品采进了先进的数字检波技术，自动增益控制技术（AGC技术），锁相环（PLL）等技术，与以同类产EAS产品相比，有性价比高，误报率低，检测率高，反应速度快，结构更加合理，性能更加稳定等优点!-EAS H9200 motherboard manual, H9200 is a used for shopping malls, clothing, supermarkets and other places of the anti-theft products, the products taken into the advanced digital detector technology, AGC Technology (AGC technology), phase-locked loop (PLL) such as technology, with production of similar products, compared EAS, there are cost-effective, low false alarm rate, detection rate, response speed, the structure more reasonable and more stable performance and so on.
Platform: | Size: 577536 | Author: | Hits:

[VHDL-FPGA-Verilog] phase_test

Description: 基于verilog的鉴相器设计，鉴相器是锁相环的一部分，功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
Platform: | Size: 1024 | Author: 林锋 | Hits:

[VHDL-FPGA-Verilog] costas

Description: costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Platform: | Size: 6144 | Author: 潇潇 | Hits:

[VHDL-FPGA-Verilog] VPD__using_FFe

Description: verilog开发一种种基于fpga的鉴相器模块 -the verilog development of all kinds based on fpga phase detector module
Platform: | Size: 447488 | Author: 房产 | Hits:

[Other] Verilog-Code

Description: Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
Platform: | Size: 7168 | Author: happyuser | Hits:

[VHDL-FPGA-Verilog] dpll1600e

Description: 数字锁相环的设计，包括鉴相器，环路滤波器，spi口输出，分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
Platform: | Size: 370688 | Author: zhujianhua | Hits:

[matlab] Phase-Locked-Loop.rar

Description: charge pump phase-locked loop with digital phase-frequency detector,charge pump phase-locked loop with digital phase-frequency detector matalab model
Platform: | Size: 456704 | Author: my name | Hits:

[LabView] Digital-phase-sensitive-detector

Description: 基于labview8.6的数字相敏检波算法源码，高精度实现测量低信噪比条件下正弦波幅值和初相的测量-Sine wave amplitude and the initial phase of the measuring low signal-to-noise ratio under the conditions measurement labview8.6-based digital phase-sensitive detection algorithm source, high-precision
Platform: | Size: 19456 | Author: 罗知亮 | Hits:

[VC/MFC] AD9850_1module

Description: 有关ＤＤＳ和鉴相器的相关资料，用来检测电路的幅频相频特性-Information about DDS and the phase detector is used to detect the amplitude and frequency of the circuit phase-frequency characteristic
Platform: | Size: 8087552 | Author: 李曼 | Hits:

[VHDL-FPGA-Verilog] DCO_ST

Description: 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
Platform: | Size: 1024 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] DPLL_TEST

Description: 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
Platform: | Size: 1024 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] dpll2

Description: 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
Platform: | Size: 1024 | Author: 朱小波 | Hits:

[LabView] Digital-phase-sensitive-detector

Description: 基于labview8.6的数字相敏检波算法源码，高精度实现测量低信噪比条件下正弦波幅值和初相的测量-Based labview8.6 digital phase-sensitive detection algorithm source code, to achieve high-precision measurement of the amplitude and the initial phase of the sine wave measured under low SNR
Platform: | Size: 215040 | Author: 潘颖 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Platform: | Size: 6144 | Author: chi zhang | Hits:

[VHDL-FPGA-Verilog] alexander

Description: Alexander phase detector and simulation objects.
Platform: | Size: 3072 | Author: nightmist | Hits:

[Other Embeded program] costas

Description: 基于costas环路的载波同步，使收发时钟频率和相位一致，环路包括四个部分乘法器和低通滤波、鉴相器、环路滤波器和数字振荡器组成-Based on the carrier synchronization of Costas loop, the frequency and phase of the transmit and receive clock is the same. The loop consists of four parts, including the multiplier and low-pass filter, phase detector, loop filter and digital oscillator.
Platform: | Size: 1024 | Author: panda | Hits:

[Program doc] pll

Description: A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is fed back toward the input forming a loop.-A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is fed back toward the input forming a loop.
Platform: | Size: 11264 | Author: mojtaba | Hits:

[SCM] ADF4002_51驱动

Description: 实现ADF4002鉴相器的51单片机驱动代码，可设置倍频及分频倍数(The 51 single chip driver code of the ADF4002 phase detector can be realized, and the frequency doubling and frequency division multiple can be set)
Platform: | Size: 27648 | Author: hahahahfff | Hits:

[matlab] pll

Description: 基于matlab的数字pll实现，鉴相器，滤波器以及压控震荡器组成，具备良好的锁相功能，适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn)
Platform: | Size: 17408 | Author: qiya2 | Hits:
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